//******************************************************************************
// Copyright(c) 2012, Hangzhou Guanglu Electronics Co., Ltd.
// All rights reserved
//
// Project Name :   SDH
// Filename     :   olb_reg.v
// Designer     :
// Email        :
// Date         :   2012-12-17
// Version      :   1.0
//
// Module Name  :   OLB_REG
// Description  :   OLB CPLD reg 
//
//
// Called by    :   OLB_CPLD_TOP
//
// Modification History`                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    
// -----------------------------------------------------------------------------
//

//`include "defines.v"


module OLB_REG
(
// input
    clk_cpld,
	reset_h,
        
    cpld_cs,
    w_r,

	cpld_addr,
    adio,    
    int,
	
	oe_test,
    soft_rst,
	rst_fpga,
	rst_cfg,
    rst_si5369,
    cksel_reg,
    cs0_c3a,
    cs1_c4a,
    
    fpga_cfg_mode,
    fpga_init,
    fpga_data_empty_flg,

    fpga_nstatus,
    fpga_conf_done,
    flg_a_set,

    mpi_par_keep,
    fpga_data_a,
    fpga_data_b,
	fpga_data_c,
	fpga_data_d,
    flg_si_set,
    si5369_data_empty_flg,
    si5369_data_a,
    si5369_data_r,
    
    
    fpga_int,
    cpld_int,
    glb_int,
    
    c3b_si_to_cpld,
    c2b_si_to_cpld,
    c1b_si_to_cpld,
    c1a_si_to_cpld,
    c2a_si_to_cpld,
    lol_si_to_cpld,
    int_alm_si_to_cpld,
    
    cs0_si_to_cpld,
    cs1_si_to_cpld,

    switch_sel3_cpld,
    switch_sel2_cpld,
    switch_sel1_cpld,
    switch_sel0_cpld,
    s155_622,
    run,
    run1,
    active_1,
    active_2,
    active_3,
    active_4,
    alm,
    alm_1,
    alm_2,
    alm_3,
    alm_4,

    test1,
	 test2
);
    

// *************************
// INPUTS and OUPUTS
// *************************
// input
input               clk_cpld;
input				reset_h;
input               cpld_cs;

input               w_r;

input	[19:0]		cpld_addr;

inout   [15:0]      adio;
input               int;

input               fpga_data_empty_flg;
input               fpga_nstatus;
input               fpga_conf_done;

input               fpga_int;
input               cpld_int;
input               glb_int;
input               c3b_si_to_cpld;
input               c2b_si_to_cpld;
input               c1b_si_to_cpld;
input               c1a_si_to_cpld;
input               c2a_si_to_cpld;
input               lol_si_to_cpld;
input               int_alm_si_to_cpld;

input               cs0_si_to_cpld;
input               cs1_si_to_cpld;

input               si5369_data_empty_flg;
output              flg_si_set;

output  [15:0]      si5369_data_a;
input   [15:0]      si5369_data_r;

output  [15:0]      mpi_par_keep;
output				oe_test;
output               soft_rst;
output				rst_fpga;
output				rst_cfg;
output              rst_si5369;
output              cksel_reg;
output              cs0_c3a;
output              cs1_c4a;
output               fpga_cfg_mode;
output               fpga_init;
output              flg_a_set; 

output  [15:0]      fpga_data_a;
output  [15:0]      fpga_data_b;
output  [15:0]      fpga_data_c;
output  [15:0]      fpga_data_d;

output              switch_sel3_cpld;
output              switch_sel2_cpld;
output              switch_sel1_cpld;
output              switch_sel0_cpld;
output              s155_622;
output              run;
output              run1;
output              active_1;
output              active_2;
output              active_3;
output              active_4;
output              alm;
output              alm_1;
output              alm_2;
output              alm_3;
output              alm_4;

output				test1;
output				test2;

reg                 rst_si5369;
reg     [15:0]      si5369_data_a;
reg                 flg_si_set;
reg                 cs0_c3a;
reg                 cs1_c4a;
reg                 cksel_reg;    

reg                 switch_sel3_cpld;
reg                 switch_sel2_cpld;
reg                 switch_sel1_cpld;
reg                 switch_sel0_cpld;
reg                 s155_622;
reg                 run;
reg                 run1;
reg                 active_1;
reg                 active_2;
reg                 active_3;
reg                 active_4;
reg                 alm;
reg                 alm_1;
reg                 alm_2;
reg                 alm_3;
reg                 alm_4;

// *************************
// INTERNAL SIGNALS
// *************************

// PARAMETERs DECLARATIONs BEGIN HERE
parameter   PCBVER      =16'h0100;
parameter   CHIPCODE    =16'h2002;
parameter   SOFTVER     =16'h0001;          
parameter   RELEASEVER  =16'h0001;
parameter   TESTVER     =16'h0001;
parameter   BDTYPEBIG   =16'hA200;
// PARAMETERs DECLARATIONs END HERE
// *************************
// CODE
// *************************
wire                oe;
wire                wr;
wire    [15:0]      adio;
reg     [15:0]      ado;

reg     [15:0]      test_reg;
reg     [15:0]      stestver;
reg                 soft_rst;
reg                 fpga_cfg_mode;
reg                 fpga_init;
reg     [15:0]      fpga_data_a;
reg     [15:0]      fpga_data_b;
reg     [15:0]      fpga_data_c;
reg     [15:0]      fpga_data_d;
reg                 flg_a_set;


reg                 fpga_int_en;
reg                 cpld_int_en;
reg                 glb_int_en;
reg     [3:0]       led;
reg                 led_alarm2;
reg                 led_alarm1;
reg                 led_alarm0;
reg                 led_runa;
reg                 led_act;
wire	[15:0]      din;

wire			    fpga_int_t;
wire				cpld_int_t;
wire				glb_int_t;

reg		[15:0]      data_tmp;
reg					rst_fpga;
reg					rst_cfg;
wire				reset_h;
reg					flg_b_set;
reg     [15:0]      mpi_par_keep;
//assign oe = ncs^noe;
//assign wr = ncs^nwe;
assign oe_test = oe;
assign oe = cpld_cs & w_r;
assign wr = cpld_cs & (~w_r);

always @(*)
begin
    if (oe == 1'b1)
        data_tmp[15:0]    <= ado[15:0] ;
//        data_tmp[15:0]    <= PCBVER ;
    else
        data_tmp[15:0]    <= 16'hzzzz ;
end

assign  adio[15:0]   = data_tmp[15:0];
assign  din[15:0]    = adio[15:0];

assign  test1 = wr;
assign  test2 = cpld_cs;

always @(posedge clk_cpld or posedge reset_h)
//always @(posedge oe or posedge reset_h)
begin            
    if(reset_h == 1'b1)
    begin
		ado[15:0] <= 16'h0000;
	end
	else
	begin
        if(oe == 1'b1)
        begin
            case(cpld_addr[5:0])
            6'h01   :   ado[15:0]   <=  PCBVER;
            6'h02   :   ado[15:0]   <=  CHIPCODE;
            6'h03   :   ado[15:0]   <=  SOFTVER;
            6'h04   :   ado[15:0]   <=  RELEASEVER;
            6'h05   :   ado[15:0]   <=  stestver[15:0];
            6'h06   :   ado[15:0]   <=  test_reg[15:0];
            6'h07   :   ado[15:0]   <=  BDTYPEBIG;
            6'h08   :   ado[15:0]   <=  {12'h000,rst_si5369,rst_cfg,rst_fpga,soft_rst};
            6'h09   :   ado[15:0]   <=  {15'h0000,fpga_cfg_mode};
            6'h0a   :   ado[15:0]   <=  {15'h0000,fpga_init};
			6'h0b   :   ado[15:0]   <=  {15'h0000,flg_a_set};
            6'h0c   :   ado[15:0]   <=  {15'h0000,fpga_data_empty_flg};
            6'h0d   :   ado[15:0]   <=  {14'h0000,fpga_nstatus,fpga_conf_done};
            6'h10   :   ado[15:0]   <=  fpga_data_a[15:0];
			6'h11	:   ado[15:0]   <=  fpga_data_b[15:0];
            6'h12   :   ado[15:0]   <=  fpga_data_c[15:0];
			6'h13   :   ado[15:0]   <=  fpga_data_d[15:0];
            6'h14   :   ado[15:0]   <= mpi_par_keep[15:0];
            
            6'h18   :   ado[15:0]   <=  {9'h000,c3b_si_to_cpld,c2b_si_to_cpld,c1b_si_to_cpld,c2a_si_to_cpld,c1a_si_to_cpld,lol_si_to_cpld,int_alm_si_to_cpld};
            6'h19   :   ado[15:0]   <=  {11'h000,cs1_si_to_cpld,cs0_si_to_cpld,cs1_c4a,cs0_c3a,cksel_reg};
            6'h1a   :   ado[15:0]   <=  si5369_data_a[15:0];
            6'h1b   :   ado[15:0]   <=  si5369_data_r[15:0];
            6'h1c   :   ado[15:0]   <=  {15'h0000,flg_si_set};
            6'h1d   :   ado[15:0]   <=  {15'h0000,si5369_data_empty_flg};
           
            6'h30   :   ado[15:0]   <=  {13'h0000,fpga_int_t,cpld_int_t,glb_int_t};
            6'h31   :   ado[15:0]   <=  {13'h0000,fpga_int_en,cpld_int_en,glb_int_en};
          
            6'h32   :   ado[15:0]   <=  {5'h00,alm_4,alm_3,alm_2,alm_1,alm,active_4,active_3,active_2,active_1,run1,run};
            6'h33   :   ado[15:0]   <=  {15'h0000,s155_622};
            6'h34   :   ado[15:0]   <=  {12'h000,switch_sel3_cpld,switch_sel2_cpld,switch_sel1_cpld,switch_sel0_cpld};
            
            default :   ado[15:0]   <=  16'h0000;
            endcase
        end
		else
		begin
			ado[15:0]   <=  16'h0000;
		end
    end
end//CPLD_RDPro

assign fpga_int_t = fpga_int|fpga_int_en;
assign cpld_int_t = cpld_int|cpld_int_en;
assign glb_int_t = glb_int|glb_int_en;

always	@(posedge clk_cpld or posedge reset_h)
begin
	if(reset_h == 1'b1)
	begin
	    stestver[15:0]  <= 16'h0000;
		test_reg[15:0]  <= 16'h0000;
		soft_rst        <= 1'b0;
		rst_fpga	 	<= 1'b0;
		rst_cfg			<= 1'b0;
        rst_si5369  	<= 1'b0;
		fpga_cfg_mode   <= 1'b0;
		fpga_init       <= 1'b0;
        flg_a_set       <= 1'b0;
		fpga_data_a[15:0] <= 16'h0000;
		fpga_data_b[15:0] <= 16'h0000;
		fpga_data_c[15:0] <= 16'h0000;
		fpga_data_d[15:0] <= 16'h0000;
        si5369_data_a[15:0] <= 16'h0000;
        flg_si_set          <= 1'b0;
    	fpga_int_en 	<= 1'b0;
    	cpld_int_en 	<= 1'b0;
    	glb_int_en  	<= 1'b0;
        cs1_c4a         <= 1'b0;
        cs0_c3a         <= 1'b0;
        cksel_reg       <= 1'b0;
        switch_sel3_cpld <= 1'b1;
        switch_sel2_cpld <= 1'b1;
        switch_sel1_cpld <= 1'b1;
        switch_sel0_cpld <= 1'b1;
        s155_622        <= 1'b0;        
        run             <= 1'b0;
        run1            <= 1'b0;
        active_1        <= 1'b0;
        active_2        <= 1'b0;
        active_3        <= 1'b0;
        active_4        <= 1'b0;
        alm             <= 1'b0;
        alm_1           <= 1'b0;
        alm_2           <= 1'b0;
        alm_3           <= 1'b0;
        alm_4           <= 1'b0;
        mpi_par_keep[15:0] <= 16'h0000;
        
	end
	else
	begin
        if(wr == 1'b1)
        begin
            case(cpld_addr[5:0])
            6'h05   :   
            begin
                stestver[15:0]  <= din[15:0];
            end
			6'h06   :   
            begin
                test_reg[15:0]  <= din[15:0];
            end
            6'h08   :   
            begin
                rst_si5369  	<= din[3];
                rst_cfg         <= din[2];
                rst_fpga		<= din[1];
                soft_rst        <= din[0];
            end
            6'h09   :   
            begin
                fpga_cfg_mode   <= din[0];
            end
            6'h0a   :   
            begin
                fpga_init       <= din[0];
            end
            6'h0b   :   
            begin
                flg_a_set       <= din[0];
            end
            6'h10   :   
            begin
                fpga_data_a[15:0] <= din[15:0];
            end
            6'h11   :   
            begin
                fpga_data_b[15:0] <= din[15:0];
            end
			6'h12   :   
            begin
                fpga_data_c[15:0] <= din[15:0];

            end
            6'h13   :   
            begin
                fpga_data_d[15:0] <= din[15:0];
            end
            6'h14   :   
            begin
                mpi_par_keep[15:0] <= din[15:0];
            end
            6'h19   :   
            begin
                cs1_c4a         <=  din[2];
                cs0_c3a         <=  din[1];
                cksel_reg       <=  din[0];
            end
            6'h1a   :   
            begin
                si5369_data_a[15:0] <= din[15:0];
            end
            6'h1c   : 
            begin
                flg_si_set  <= din[0];
            end


            6'h31   :   
            begin
                fpga_int_en <= din[2];
                cpld_int_en <= din[0];
                glb_int_en  <= din[1];
            end
            
            6'h32   :   
            begin
                alm_4           <= din[10];
                alm_3           <= din[9];
                alm_2           <= din[8];
                alm_1           <= din[7];
                alm             <= din[6];
                active_4        <= din[5];
                active_3        <= din[4];
                active_2        <= din[3];
                active_1        <= din[2];
                run1            <= din[1];
                run             <= din[0];
            end
            6'h33   :   
            begin
                s155_622        <= din[0];        
            end
            6'h34   :   
            begin
                switch_sel3_cpld <= din[3];
                switch_sel2_cpld <= din[2];
                switch_sel1_cpld <= din[1];
                switch_sel0_cpld <= din[0];
            end
            
            
            default : 	;
            endcase
        end
	end
end
endmodule